Semiconductor components must be tested following the fabrication process. For testing small, thin components, such as bare dice and chip scale packages, test carriers can be utilized to temporarily package the components. One type of test is referred to as burn-in and involves heating a component for several hours while test signals are applied to integrated circuits on the component. This type of test carrier is disclosed in U.S. Pat. Nos. 5,519,332; 5,541,525; 5,495,179; 5,440,240; and 5,408,190 to Wood et al.
Typically the component being tested includes external contacts, such as bond pads on bare dice, or ball grid array (BGA) solder balls on chip scale packages. An interconnect component of the test carrier includes contacts for establishing temporary electrical connections with the external contacts on the component.
The test carrier also includes a base with terminal contacts that electrically connect to a test apparatus such as a test socket or test board. The test apparatus is in electrical communication with test circuitry configured to transmit test signals to the integrated circuits. During assembly of the carrier, separate electrical paths are formed between the terminal contacts on the base, and the contacts on the interconnect. One method for making these electrical paths is by forming the base and interconnect with metal conductors, and then wire bonding the conductors on the base, to conductors on the interconnect.
One aspect of these carrier is that the external contacts on semiconductor components are becoming smaller and more closely spaced. Accordingly, the electrical paths through the test carriers to the components are becoming more closely spaced. Also signal transmission speeds through the electrical paths are increasing. For example, some integrated circuits operate at clocking speeds of 500 mhz or more and must be tested at these speeds.
One problem occurring during testing at high speeds is referred to as "parasitic inductance". For example, parasitic inductance can result from switching transients and cross coupling between the conductors on the base or interconnect of the test carrier. Parasitic inductance can also result from cross coupling of the bond wires between the interconnect and base. The parasitic inductance can cause spurious signals and a drop or modulation in the power supply voltage, that is sometimes referred to as power supply noise. Parasitic inductance, and the resultant spurious signals and power supply noise, can degrade the operation of the semiconductor component and adversely affect the test results.
The test circuitry typically includes decoupling capacitors to help alleviate parasitic inductance generated within the test circuitry. However, parasitic inductance can also occur in the electrical paths between the test circuitry and the test carrier. For example parasitic inductance can occur in the test socket or test board.
Another prior art method for reducing parasitic inductance and power supply noise is by mounting decoupling capacitors directly to the test socket. For example, semiconductor devices packaged in conventional packages, such as small outline j-lead packages (SOJs), or dual in-line packages (DIPs), are typically tested by insertion into sockets on the test board. For reducing parasitic inductance during testing, a thin film capacitor can be mounted between the socket and the semiconductor package. U.S. Pat. No. 5,844,419 to Akram et al., discloses a thin film capacitor configured for mounting to a test socket in direct electrical contact with the power and ground leads for the package.
Similarly, a thin film capacitor could be configured for insertion between the test board, and a test carrier for testing bare dice and chip scale packages. However, parasitic inductances can still arise within the test carrier. The present invention is directed to a test carrier which addresses the problem of parasitic inductance occurring within the test carrier.